
ISL12022
7
FN6659.3
November 22, 2011
SDA vs SCL Timing
Symbol Table
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF
tLOW
tBUF
tAA
tR
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Will be steady
May change
from LO W
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LO W
Will change
from HIGH
to LOW
Don’t Care:
Changes Allowed
Changing:
State Not Known
N/A
Center Line is
High Impedance
FIGURE 2. STANDARD OUTPUT LOAD FOR TESTING THE DEVICE
WITH VDD = 5.0V
SDA
AND
IRQ/FOUT
1533
Ω
100pF
5.0V
FOR VOL= 0.4V
AND IOL = 3mA
EQUIVALENT AC OUTPUT LOAD CIRCUIT FOR VDD = 5V